Dr. Shivam Verma

Associate Professor
Department of Electronics Engineering
Email:
shivam.ece@iitbhu.ac.in
Phone(s):
05427165447
Area of Interest:
Neuromorphic Computing, Spintronics, Devices and Circuits for VLSI, Non-volatile memory and logic circuits

Dr Shivam Verma is an Associate Professor in the Department of Electronics Engineering at IIT (BHU) Varanasi, with expertise in microelectronics, VLSI design, and emerging memory technologies. He obtained his Ph.D. in Microelectronics and VLSI from IIT Roorkee in 2017. He completed his M.Tech. with Honours in Microelectronics from IIT (BHU) Varanasi in 2012 and his B.E. in Electronics and Communication Engineering from Shri Vaishnav Institute of Technology and Science, Indore, in 2010. His research focuses on neuromorphic computing, spintronics, and non-volatile memory and logic devices, with an emphasis on developing energy-efficient, next-generation computing hardware by integrating novel devices with circuit design.

Ph.D. (Microelectronics and VLSI) 
Dissertation: Design of Spin Transfer Torque-Based Memory and Logic,
Indian Institute of Technology, Roorkee, 2017.

M. Tech. (with Hons.),
Specialization: Microelectronics, 
Indian Institute of Technology (BHU), Varanasi, 2012.

AIR-429 in GATE 2010, with a GATE Score of 741

B. E. (Electronics and Communication Engineering),
Shri Vaishnav Institute of Technology and Science, Indore, M.P, 2010

List of Publications

  Journals

  1. Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Modeling of In-Plane Magnetic Tunnel Junction for Mixed Mode Simulations,” IEEE Trans. on Magnetics, vol. 50, no. 8, Mar. 2014.

  2. Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Novel 4F2 Buried Source Line STT MRAM Cell with Vertical GAA Transistor as Select Device,” IEEE Trans. on Nanotechnology, vol. 13, no. 6, pp. 1163–1171, 2014.

  3. Shivam Verma, M. Satyanarayana Murthy, and Brajesh Kumar Kaushik, “All Spin Logic (ASL): A Micromagnetic Perspective,” IEEE Trans. on Magnetics, vol. 51, no. 10, pp. 3400710-1–3400710-7, 2015.

  4. Shivam Verma, and Brajesh Kumar Kaushik, “Low Power High Density STT MRAMs on 3D Vertical Silicon Nano-wire Platform,” IEEE Trans. on VLSI Systems, vol. 24, no. 4, pp. 1371–1376, 2015.

  5. Shivam Verma, Pankaj Kumar Pal, Sanjay Mahawar, and Brajesh Kumar Kaushik, “Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” IEEE Trans. on Electron Devices, vol. 63, no. 7, pp. 2771–2776, 2016.

  6. Shivam Verma, Anant. A. Kulkarni, and Brajesh Kumar Kaushik, “Spintronics-Based Devices to Circuits: Perspectives and Challenges,” IEEE Nanotechnology Magazine, vol. 10, no. 4, pp. 13-28, 2016.

  7. A Kulkarni, S Prajapati, Shivam Verma, and Brajesh Kumar Kaushik, “Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based n-Qubit Architecture,” IEEE Trans. on Magneticsvol. 54, no. 10, Oct. 2018.

  8. S. Prajapati, Shivam Verma, A. A. Kulkarni, and Brajesh Kumar Kaushik, “Modeling of magnetic tunnel junction for multilevel STT-MRAM cell,” IEEE Trans. on Nanotechnology, vol. 18, pp. 1005-1014, 2019.

  9. Shivam Verma, Ravneet Paul, and Mayank Shukla, “Non-volatile Latch Compatible with Static and Dynamic CMOS for Logic in Memory Applications,” IEEE Trans. on Magnetics, vol. 58, pp. 1-8, 2022.

  10. Roopesh Singh, Shivam Verma, and Sushant Mittal, “FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement,” IEEE Trans. on Electron Devices, vol. 69, no. 12, pp. 6699–6704, 2022.

  11. Jagadish Rajpoot, and Shivam Verma, “Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 70, no. 7, pp. 2630-2634, 2023. 

  12. Jagadish Rajpoot, Ravneet Paul, and Shivam Verma, “SPICE-Based Compact Model for Voltage-induced Magnetocapacitance in Magnetic Tunnel Junctions,” IEEE Trans. on Magnetics, vol. 59, no. 9, pp. 1-8, 2023. 

  13. Ashok Kumar, Jagadish Rajpoot, and Shivam Verma, “Design Space Exploration and Power Optimization of STT MRAM using Trimmed Fin Asymmetric FinFET ,” Microelectronics Journal: Elsevier, vol. 149, no. 106238, pp. 1-9, 2024. 

  14. Roopesh Singh, Sushant Mittal, Shivam Verma, Junctionless Accumulation-Mode SOI Ferroelectric FinFET for Synaptic Weights, Microelectronics Journal: Elsevier, vol. 153, no. 106413, pp. 1-8, 2024. 

  15. Roopesh Singh, and Shivam Verma, "Memristive Ferroelectric FET for 1T-1R Nonvolatile Memory with Non-Destructive Readout", IEEE Open Journal of Nanotechnology, vol. 6, pp. 27-34, Jan. 2025, doi: 10.1109/OJNANO.2025.3531759. 

  16. Jagadish Rajpoot, Prem Prakash Mangalam, Abhijit Chaterjee, Upamannu Sen, Parul Singh, and Shivam Verma, "An Area-Efficient with High-Dynamic Range Readout Circuit for Resistive Gas Sensors," Journal of Circuits, Systems, and Computers, World Scientific, 2025. https://doi.org/10.1142/S0218126625502780

  17. Richa Baranwal, Atul S. M. Tripathi, Abhijit Chaterjee, Upamannu Sen, Parul Singh, V. N. Mishra, and Shivam Verma, "Fabrication and Characterization of PDPP2T-TT Thin Film FET-based NH3 Gas Sensor at Room Temperature," Optical Materials, Elsevier, vol. 166, Sep. 2025

  18. Jagadish Rajpoot, and Shivam Verma, "Efficient and reliable hybrid MTJ/CMOS-based logic-in-memory architecture using SHE-MTJ," Journal of Computational Electronics, Springer Nature, vol. 24, no. 108, 2025. https://doi.org/10.1007/s10825-025-02359-6

  19. V. P. Singh, S. M. Yadav, Shivam Verma and A. Pandey, "Cu2MoS4 Nanosheets via Solvothermal Synthesis for High-Performance Ag/Cu2MoS4/Ag MSM Photodetector," in IEEE Photonics Technology Letters, (In press) doi: 10.1109/LPT.2025.3619846.

  20. V. P. Singh, S. M. Yadav, Shivam Verma and A. Pandey, "Facile Solvothermal Synthesis of Cu2MoS4 Nanosheets: Enabling Efficient UV–Visible Photodetection," in IEEE Transactions on Electron Devices, (In press) doi: 10.1109/TED.2025.3619917.

  21. Roopesh Singh, Alok Kumar Tripathi, and Shivam Verma, "Device circuit co-design of novel non-volatile latch using junctionless ferroelectric FET," Analog Integrated Circuits and Signal Processing, Springer Nature, 2025.  

  22. Anant Aravind Kulkarni, Shivam Verma, “Inequal Three Qubit Entanglement Using GHZ State Generation for Spin-Torque Based Qubit Architecture”, IEEE Open Journal of Nanotechnology, vol. 6, pp. 179-186, Dec 2025

  23. Jagadish Rajpoot, Shivam Verma, “Compact STT/SHE-MTJ Model with Monte-Carlo Independent Thermal Noise”, Journal of Physics: Conference Series, Vol. 3161, Jan. 2026

  24. Nikhil, Richa Baranwal, Shivam Verma, Srinu Gangolu. “Molecularly Ordered PBTTT/Au-rGO Films for Mobility-Enhanced OFET Ammonia Sensors”, ACS Applied Polymer Materials, vol. 8, pp. 3432-3444, Feb. 2026

  25. Nikhil, Radhe Shyam, Richa Baranwal, Shivam Verma, Srinu Gangolu, “Enhanced Coherence Length and Optical Disorder in PBTTT/SnS2 Composites: A Structure–Property Analysis for NO2 Sensing”, ACS Applied Electronic Materials, vol. 8, pp. 3843-3856, Apr. 2026

  26. Radhe Shyam, Richa Baranwal, Shivam Verma, Bhola Nath Pal, Rajiv Prakash, “Unveiling fluoro and alkyl derivatives of polythiophene for highly sensitive ammonia gas sensing based on unidirectional thin film channel OTFT”. Surfaces and Interfaces, Elsevier, Vol. 91, June 2026

Conferences

  1. Sanjay Mahawar, Shivam Verma, Pankaj Kumar Pal, and Brajesh Kumar Kaushik, “High Reliability STT MRAM using Fully Depleted Body and 4H–SiC Buried Oxide NMOS,” in Proc. IEEE 11th International Conference on Electron Devices & Solid-State Circuits (EDSSC 2015), Singapore, pp. 705-708, June 1-4, 2015.

  2. Shivam Verma, Sanjay Mahawer, and Brajesh Kumar Kaushik, “Low Power STT MRAM Cell With Asymmetric Drive Current Vertical GAA Select Device,” in Proc. 12th IEEE International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2015), Hua Hin, Thailand, pp. 1-5, June 24-27, 2015.

  3. Pankaj Kumar Pal, Shivam Verma, Brajesh Kumar Kaushik, and Sudeb Dasgupta, “Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design,” in Proc. IEEE 11th International Conference on Electron Devices & Solid-State Circuits (EDSSC 2015), Singapore, pp. 705-708, June 1-4, 2015.

  4. Sanjay Prajapati, Shivam Verma, Anant Aravind Kulkarni, and Brajesh Kumar Kaushik, “Novel compact model for multi-level spin torque magnetic tunnel junctions,” in Proc. SPIE 9931, Spintronics IX, San Diego, CA, USA, August 28, 2016.

  5. Shivam Verma, “Novel Hybrid MTJ-CMOS Based Programmable Gain Amplifier for Portable Applications,” in Proc. 4th IEEE International Conference on Electron Devices Technology & Manufacturing Conference (EDTM2020, Penang, Malaysia, 6-21 April, 2020.

  6. Shivam Verma, “Multilayer Micromagnetic Models for All Spin Logic,” in Proc. 17th IEEE India Council International Conference (INDICON) 2020, New Delhi, India, 10-13 December, 2020.

  7. Roopesh Singh, Sumit Purkait, and Shivam Verma, “Junction Less Ferroelectric FET on FDSOI for Non-Volatile Logic-In-Memory Applications,” in Proc. 6th IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, 11-14 December, 2022.

  8. Jagadish Rajpoot, Meghna Gupta, and Shivam Verma, “Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination” in Proc. 30th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Penang, Malaysia, 24-27 July 2023.

  9. Kirti, Shivam Verma, and Somak Bhattacharyya, “A High-Gain Ku-Band Low Noise Amplifier (LNA) with Ultra-Low Noise Figure” in Proc. IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), Ahmedabad, India, 11-14 December 2023. 
    DOI: 10.1109/MAPCON58678.2023.10463994

  10. Kirti, Shivam Verma, and Somak Bhattacharyya, “Design and Implementation of a High-Gain Ku-Band Low Noise Amplifier” in Proc. 2024 11th IEEE Up Section International Conference on Electrical Electronics and Computer Engineering, Lucknow, India, 29 Nov.-1 December 2024. 

  11. Ashok Kumar, Roopesh Singh, Shivam Verma, “Design and Simulation of a Quadruple Channel Fin-FET Using T-CAD”, in Proc. EAI International Conference on Body Area Networks, Varanasi, India, 15-16 December 2024. 
  12. Kirti, Shivam Verma, and Somak Bhattacharyya, “An Adaptive Hybrid-Mode GaN MMIC Power Amplifier for 5G Communication Network”, in Proc. 2025 IEEE Wireless Antenna and Microwave Symposium (WAMS), Kancheepuram, Chennai, India, 5 June- 8 June, 2025

  13. Kirti, Shivam Verma, and Somak Bhattacharyya, “Design of a Gain-Stabilized Ka-Band Low Noise Amplifier (LNA)” in Proc. 2025 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), Kochi, India, 14–18 December 2025. 

  14. Vartika Singh, Roopesh Singh, Shivam Verma, “Neuromorphic Computing Using Nonvolatile Memory Devices: A Case Study” in Proc. 2025 First International Conference on Intelligent Computing and Systems at the Edge (ICEdge), Bangalore, India, 18–20 December 2025.

  15. Jitendra Krishna Arya, Richa Baranwal, VN Mishra, Shivam Verma, “Fabrication and Characterization of a Self-aligned FFTM-processed OFET Device for High-current Applications” in Proc. 2026 23rd International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), Chonburi, Thailand, May 27-30, 2026.

  1. B. K. Kaushik and Shivam VermaSpin Transfer Torque Based Devices, Circuits and MemoryArtech Press, Norwood, MA, USA, 2016.

  2. B. K. Kaushik, Shivam Verma, Anant Kulkarni, and Sanjay Prajapati, Next Generation Spin Torque Memories, Springer Nature, USA, 2017

Committees

  • Convener DUGC from September 2023 to August 2025
  • Member DPGC from September 2020 to August 2022, September 2023 to September 2024
  • Member DUGC from September 2020 to  August 2022

Courses:
 

Level 

Course No. & Title

No. of Students (approx.)

Year (Semester)

U.G.

EC-431, Basic VLSI Design

 100

2019-20 (Odd)

U. G

EC-433, Advanced Field Effect Devices

39

2019-20 (Even)

U. G

EO-203, Digital Circuits and Systems

127

2019-20 (Even)

U. G

EC-431, Basic VLSI Design

88

2020-2021 (Odd)

U. G

EC-331, Microelectronics

125

2020-2021 (Odd)

P.G.

EC-572, LSI/VLSI Design

30

2020-2021 (Even)

P.G.

EC-571, Heterojunction Devices and Technology

20

2020-2021 (Even)

U.G.

EC-431, Basic VLSI Design

100

2021-2022 (Odd)

U.G.

EC-301, Digital Circuits and Systems

160

2021-2022 (Odd)

P.G.

EC-572, LSI/VLSI Design

30

2021-2022 (Even)

P.G.

EC-571, Heterojunction Devices and Technology

20

2021-2022 (Even)

U.G.

EC-431, Basic VLSI Design

125

2022-2023 (Odd)

U.G.

EC-331, Microelectronics

140

2022-2023 (Odd)

P.G. 

EC-572, LSI/VLSI Design

30

2022-2023 (Even)

P.G.

EC-571, Heterojunction Devices and Technology

20

2022-2023 (Even)

U.G.

EC-431, Basic VLSI Design

145

2023-24 (Odd)

U.G.

EC-432 VLSI Technology

31

2023-24 (Odd)

P.G.

EC-572, LSI/VLSI Design

30

2023-24 (Even)

U.G.

EC-102 Electronic Circuit Workshop

145

2023-24 (Even)

U.G.

EC-431, Basic VLSI Design

145

2024-25 (Odd)

P.G.

EC-572, LSI/VLSI Design

30

2024-25 (Even)

U.G.

EC-102 Electronic Circuit Workshop

145

2024-25 (Even)

U.G.

EC-431, Basic VLSI Design

148

2025-26 (Odd)

P.G.

EC 501 Chip Design Fundamentals 

17

2025-26 (Odd)

P.G.

EC-571, Heterojunction Devices and Technology

18

2025-26 (Even)

  • Associate Professor in the Department of Electronics Engineering, IIT (BHU), Varanasi, since 27th February 2026
  • Assistant Professor (Grade-I) in the Department of Electronics Engineering, IIT (BHU), Varanasi, from 02nd May 2020 to 26th February 2026
  • Assistant Professor (Grade-II) in the Department of Electronics Engineering, IIT (BHU), Varanasi from 27th August 2019 to 01st May 2020
  • Assistant Professor (Grade-II) in ECE Department, NIT Warangal, India from June 2018 to August 2019
  • Assistant Professor in EEE Department, BITS Pilani, K. K. Birla Goa Campus, Goa, India from May 2017 to May 2018

Books Reviewed and Reviewer Assignments

  • "Electronic Devices and Circuits" a second year diploma level book as per AICTE's Model Curriculum available at (Link: https://ekumbh.aicte-india.org/)
  • "VLSI Design" a third year degree book as per AICTE's Model Curriculum (Under review)

 

Articles Reviewed (Tentative)

  • IEEE Transaction of Electron Devices: 5+
  • IEEE Transaction of Circuits and Systems Brief: 2
  • IEEE Transaction of Magnetics: 10+
  • IEEE Transaction on Nanotechnology: 2+
  • IEEE Transaction on VLSI Systems: 1
  • Microelectronics Journal, Elsevier:2
  • Journal of Electronic Materials: 1
  • Others: 10+

Google Scholar:  https://scholar.google.co.in/citations?user=pyB8nJcAAAAJ&hl=en

Researcher ID: https://www.webofscience.com/wos-researcher-cv/public/3562842/cc7840a1-110e-4c08-a544-a51668163e27/SHIVAMVERMA_Web_of_Science_Researcher_CV.pdf

Looking for bright young candidates with external fellowships for Ph.D. 

If interested email your CV to shivam.ece@iitbhu.ac.in

Candidates interested in QIP Admissions are requested to contact me via email if interested in high-quality/imact research in the area of Microelectronics and VLSI.

Or contact me by phone on  70146 81827

https://drive.google.com/file/d/1VU9AqppAtpWUWcqWQ10IhprkYdC28TLx/view?usp=sharing

Ph.D. Thesis Supervised:     

Names of Students

Date of registration

Date of thesis submission

Date of defence

Guide or Co-Guide

Mr. Jagadish(19091501)

January 2020

12-09-2024

07-01-2025

Guide

Mr. Roopesh Singh (20091503)

January 2021

21-03-2025

13-09-2025

Guide

Mr. Ashok Kumar (21091003)

 July 2021

Ongoing

--

Guide

Ms. Kirti

2021

Ongoing

---

Co-Guide

Mr. Vikram Pratap Singh(23091004)

July2023

Ongoing

---

Co-Guide

Mr. Jitendra Krishna Arya (24091017)

July 2024

Ongoing

---

Guide

Mrs. Richa Baranwal

July 2024

Ongoing

---

Co-Guide

Mr. Akash Kumar Gupta (25091002) 

July 2025

Ongoing

---

Guide

Ms. Akanksha Verma (25091001)

July 2025

Ongoing

---

Co-Guide

M.Tech. Thesis Supervised: 

Name of Students

Supervisor or Co-Supervisor

Date of Completion

Mr. Mayank Shukla (19092003)

Supervisor

19-07-2021

Mr. Punit Kumar Mishra (19092004)

Supervisor

24-07-2021

Mr. Vaibhav Gupta (19092020)

Supervisor

19-07-2021

Mr. Kushal Gangwar (19092024)

Supervisor

19-07-2021

Mr. Prashant Kumar Singh (20092027)

Supervisor

12-07-2022

Mr. Ravneet Paul (20092033)

Supervisor

12-07-2022

Mr. Shyam Subba (20092038)

Supervisor

12-07-2022

Mr. Sumit Purkait (20092032)

Supervisor

12-07-2022

Mr. Alok Tripathi (21092004)

Supervisor

26-06-2023

Ms. Meghna Gupta (21092005)

Supervisor

15-06-2023

Mr. Prem Prakash Mangalam (22092011)

Supervisor

15-07-2024

Mr.  Suraj Verma ((23092031)

Supervisor

Sept 2025

Open Source Spintronic MTJ model library

(COPY and PASTE the link in your browser)

https://github.com/SHIVAMVERMAID/Spintronic-MTJ-model-library.git

Go through our latest models for Magnetic Tunnel Junction Devices fully compatible with open source NGSPICE simulation software

 

Please cite any one of the following if you use in your publication.

Rajpoot, J., Paul, R. and Verma, S., 2022. Novel STT/SHE MTJ Compact Model Compatible with NGSPICE. arXiv preprint arXiv:2208.14055.

Jagadish Rajpoot, Ravneet Paul, and Shivam Verma, "SPICE-Based Compact Model for Voltage Induced Magnetocapacitance in Magnetic Tunnel Junctions," IEEE Transactions on Magnetics, vol. 59, no. 9, pp. 1-8, Sept. 2023, Art no. 7200108, doi: 10.1109/TMAG.2023.3296830.

Jagadish Rajpoot, and Shivam Verma "Compact STT/SHE-MTJ Model with Monte-Carlo Independent Thermal Noise," IOP Journal of Physics: Conference Series, (Gold open access Journal, in press).