Ph.D. (Microelectronics and VLSI) 
Dissertation: Design of Spin Transfer Torque Based Memory and Logic,
Indian Institute of Technology, Roorkee, 2017.

M. Tech. (with Hons.),
Specialization: Microelectronics, 
Indian Institute of Technology (BHU), Varanasi, 2012.

AIR-429 in GATE 2010, with GATE Score of 741

B. E. (Electronics and Communication Engineering),
Shri Vaishnav Institute of Technology and Science, Indore, M.P, 2010

List of Publications

  Journals

• Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Modeling of In-Plane Magnetic Tunnel Junction for Mixed Mode Simulations,” IEEE Trans. on Magnetics, vol. 50, no. 8, Mar. 2014.
• Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Novel 4F² Buried Source Line STT MRAM Cell with Vertical GAA Transistor as Select Device,” IEEE Trans. on Nanotechnology, vol. 13, no. 6, pp. 1163–1171, 2014.
• Shivam Verma, M. Satyanarayana Murthy, and Brajesh Kumar Kaushik, “All Spin Logic (ASL): A Micromagnetic Perspective,” IEEE Trans. on Magnetics, vol. 51, no. 10, pp. 3400710-1–3400710-7, 2015.
• Shivam Verma, and Brajesh Kumar Kaushik, “Low Power High Density STT MRAMs on 3D Vertical Silicon Nano-wire Platform,” IEEE Trans. on VLSI Systems, vol. 24, no. 4, pp. 1371–1376, 2015.
• Shivam Verma, Pankaj Kumar Pal, Sanjay Mahawar, and Brajesh Kumar Kaushik, “Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” IEEE Trans. on Electron Devices, vol. 63, no. 7, pp. 2771–2776, 2016.
• Shivam Verma, Anant. A. Kulkarni, and Brajesh Kumar Kaushik, “Spintronics based Devices to Circuits: Perspectives and Challenges,” IEEE Nanotechnology Magazine, vol. 10, no. 4, pp. 13-28, 2016.
• A Kulkarni, S Prajapati, Shivam Verma, and Brajesh Kumar Kaushik, “Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based n-Qubit Architecture,” IEEE Trans. on Magnetics, vol. 54, no. 10, Oct. 2018.
• S. Prajapati, Shivam Verma, A. A. Kulkarni, and Brajesh Kumar Kaushik, “Modeling of magnetic tunnel junction for multilevel STT-MRAM cell,” IEEE Trans. on Nanotechnology, vol. 18, pp. 1005-1014, 2019.
• Shivam Verma, Ravneet Paul, and Mayank Shukla, “Non-volatile Latch Compatible with Static and Dynamic CMOS for Logic in Memory Applications,” IEEE Trans. on Magnetics, vol. 58, pp. 1-8, 2022.
• Roopesh Singh, Shivam Verma, and Sushant Mittal, “FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement,” IEEE Trans. on Electron Devices, vol. 69, no. 12, pp. 6699–6704, 2022.
• Jagadish Rajpoot, and Shivam Verma, “Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 70, no. 7, pp. 2630-2634, 2023. 
• Jagadish Rajpoot, Ravneet Paul, and Shivam Verma, “SPICE Based Compact Model for Voltage-induced Magnetocapacitance in Magnetic Tunnel Junctions,” IEEE Trans. on Magnetics, vol. 59, no. 9, pp. 1-8, 2023. 
• Ashok Kumar, Jagadish Rajpoot, and Shivam Verma, “Design Space Exploration and Power Optimization of STT MRAM using Trimmed Fin Asymmetric FinFET ,” Microelectronics Journal: Elsevier, vol. 149, no. 106238, pp. 1-9, 2024. 
• Roopesh Singh, Sushant Mittal, Shivam Verma, Junctionless Accumulation-Mode SOI Ferroelectric FinFET for Synaptic Weights, Microelectronics Journal: Elsevier, 2024 (Early Access) https://authors.elsevier.com/a/1jq5G6hIXqRo6O.

Conferences

1. Sanjay Mahawar, Shivam Verma, Pankaj Kumar Pal, and Brajesh Kumar Kaushik, “High Reliability STT MRAM using Fully Depleted Body and 4H–SiC Buried Oxide NMOS,” in Proc. IEEE 11^th International Conference on Electron Devices & Solid-State Circuits (EDSSC 2015), Singapore, pp. 705-708, June 1-4, 2015.
2. Shivam Verma, Sanjay Mahawer, and Brajesh Kumar Kaushik, “Low Power STT MRAM Cell With Asymmetric Drive Current Vertical GAA Select Device,” in Proc. 12th IEEE International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2015), Hua Hin, Thailand, pp. 1-5, June 24-27, 2015.
3. Pankaj Kumar Pal, Shivam Verma, Brajesh Kumar Kaushik, and Sudeb Dasgupta, “Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design,” in Proc. IEEE 11th International Conference on Electron Devices & Solid-State Circuits (EDSSC 2015), Singapore, pp. 705-708, June 1-4, 2015.
4. Sanjay Prajapati, Shivam Verma, Anant Aravind Kulkarni, and Brajesh Kumar Kaushik, “Novel compact model for multi-level spin torque magnetic tunnel junctions,” in Proc. SPIE 9931, Spintronics IX, San Diego, CA, USA, August 28, 2016.
5. Shivam Verma, “Novel Hybrid MTJ-CMOS Based Programmable Gain Amplifier for Portable Applications,” in Proc. 4^th IEEE International Conference on Electron Devices Technology & Manufacturing Conference (EDTM) 2020, Penang, Malaysia, 6-21 April, 2020.
6. Shivam Verma, “Multilayer Micromagnetic Models for All Spin Logic,” in Proc. 17th IEEE India Council International Conference (INDICON) 2020, New Delhi, India, 10-13 December, 2020.
7. Roopesh Singh, Sumit Purkait, and Shivam Verma, “Junction Less Ferroelectric FET on FDSOI for Non-Volatile Logic-In-Memory Applications,” in Proc. 6th IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, 11-14 December, 2022.
8. Jagadish Rajpoot, Meghna Gupta, and Shivam Verma, “Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination” in Proc. 30th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Penang, Malaysia, 24-27 July 2023.

Books

1. B. K. Kaushik and Shivam Verma, Spin Transfer Torque Based Devices Circuits and Memory, Artech Press, Norwood, MA, USA, 2016.
2. B. K. Kaushik, Shivam Verma, Anant Kulkarni, and Sanjay Prajapati, Next Generation Spin Torque Memories, Springer Nature, USA, 2017.

Principal Investigator

Co-Principal Investigator

Committees

• Convener DUGC from 9th September 2023 to till date
• Member DPGC from 1st September 2020 to 31st August 2022, 9th September 2023 to till date
• Member DUGC from 1st September 2020 to 31st August 2022

Courses:
 

• Assistant Professor (Grade-I) in the Department of Electronics Engineering, IIT (BHU), Varanasi since 02nd May 2020
• Assistant Professor (Grade-II) in the Department of Electronics Engineering, IIT (BHU), Varanasi from 27th August 2019 to 01st May 2020
• Assistant Professor (Grade-II) in ECE Department, NIT Warangal, India from June 2018 to August 2019
• Assistant Professor in EEE Department, BITS PIlani, K. K. Birla Goa Campus, Goa, India from May 2017 to May 2018

Books Reviewed and Reviewer Assignments

• "Electronic Devices and Circuits" a second year diploma level book as per AICTE's Model Curriculum available at (Link: https://ekumbh.aicte-india.org/)
• "VLSI Design" a third year degree book as per AICTE's Model Curriculum (Under review)

Articles Reviewed (Tentative)

• IEEE Transaction of Electron Devices: 5+
• IEEE Transaction of Circuits and Systems Brief: 2
• IEEE Transaction of Magnetics: 10+
• IEEE Transaction on Nanotechnology: 2+
• IEEE Transaction on VLSI Systems: 1
• Microelectronics Journal, Elsevier:2
• Journal of Electronic Materials: 1
• Others: 10+

Google scholar:  https://scholar.google.co.in/citations?user=pyB8nJcAAAAJ&hl=en

Reasearcher ID: https://www.webofscience.com/wos-researcher-cv/public/3562842/cc7840a1-110e-4c08-a544-a51668163e27/SHIVAMVERMA_Web_of_Science_Researcher_CV.pdf

Looking for bright young candidates with external fellowships for Ph.D. 

If interested email your CV to shivam.ece@iitbhu.ac.in

Candidates interested in QIP Admissions are requested to contact me through email if interested in high quality/imact research in area of Microelectronics and VLSI.

Or contact me through phone on 9336748106.

https://drive.google.com/file/d/1VU9AqppAtpWUWcqWQ10IhprkYdC28TLx/view?usp=sharing