भारतीय प्रौद्योगिकी संस्थान (का.हि.वि.) वाराणसी

• Assistant Professor, Department of Electronics Engineering, IIT (BHU) Varanasi, India (July, 2026 - till date)
• Project Scientist (2024-2025) & National Post-Doctoral Fellow (NPDF) (2025-2026), IISc Bangalore, India 
  • Mentor: Dr. Debayan Das
  • Project: RISC-V-Assisted Hardware Software Co-Design of Novel, Efficient and Power/Electro-Magnetic Side Channel Attack-Secure Post-Quantum Cryptographic CRYSTALS Kyber and Dilithium
  • Funding agency: Anusandhan National Research Foundation (ANRF), Department of Science & Technology, Govt. of India
• Associate Project Engineer, IIT Guwahati, India (2022-2024)
  • Project title: Securing low power embedded processors for IoT applications against power analysis attacks
  • Supervisor: Prof. Roy Paily Palathinkal 
  • Funding agency: Semiconductor Research Corporation (SRC), USA
• Associate Project Engineer, IIT Guwahati, India (2016)
  • Project title: Air Quality Monitoring System
  • Supervisors: Prof. Roy Paily Palathinkal & Dr. Nagarjuna Nallam
  • Funding agency: Ministry of Electronics and Information Technology (MeitY), Govt. of India
• Assistant Professor, Department of Electronics & Instrumentation Engineering, NIT Silchar, India (2014-2016)
  • Undergrad courses taught: 
    • Theory: Basic Electronics, Analog Electronics, Electro Magnetic Field Theory, Communication & Telemetry 
    • Lab: Analog Electronics, Microprocessors, Communication Systems 
  • Postgrad courses taught: 
    • Theory: IC & VLSI Design, Real Time Operating System

• Project title: RISC-V-Assisted Hardware Software Co-Design of Novel, Efficient and Power/Electro-Magnetic Side Channel Attack-Secure Post-Quantum Cryptographic CRYSTALS Kyber and Dilithium

  • Role: Principal Investigator (PI)

  • Funding agency: Anusandhan National Research Foundation (ANRF), Department of Science and Technology, Govt. of India

  • Sanctioned amount: 30.96 lakhs INR

  • Duration: Nov. 2025 - Oct. 2027

Journals

• T. B. Singha, R. P. Palathinkal and S. R. Ahamed, "Securing AES Designs Against Power Analysis Attacks: A Survey," in IEEE Internet of Things Journal, vol. 10, no. 16, pp. 14332-14356, 15 Aug.15, 2023, doi: 10.1109/JIOT.2023.3265683.

• T. B. Singha, B. Sanjana, T. M. Ignatius, R. P. Palathinkal and S. R. Ahamed, "Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 11, pp. 2149-2153, Nov. 2024, doi: 10.1109/TVLSI.2024.3422501.

• T. B. Singha, R. P. Palathinkal and S. R. Ahamed, "Analysis of S-box hardware resources to improve AES intrinsic security against power attacks," in IEEE Embedded Systems Letters, vol. 16, no. 4, pp. 525-528, Dec. 2024, doi: 10.1109/LES.2024.3478070.

• A. Kumari, T. M. Ignatius, T. B. Singha and R. P. Palathinkal, "Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2026.3720299.

• V. Padmakumar, T. Mary Ignatius, T. Birjit Singha, R. Paily Palathinkal and S. Rafi Ahamed, "Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks," in IEEE Embedded Systems Letters, vol. 17, no. 1, pp. 10-13, Feb. 2025, doi: 10.1109/LES.2024.3420226.

• T. M. Ignatius, T. Birjit Singha and R. Paily Palathinkal, "Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications," in IEEE Access, vol. 12, pp. 150230-150248, 2024, doi: 10.1109/ACCESS.2024.3477961.

• L. Jain, T.B. Singha and B. Kant, 2013. Interrupt Based RC5 Remote-decoding Using 8051 μC. Journal of Artificial Intelligence, 6: 187-190.

Conferences

• Owi Hemant Mahajan, Riya Riya, Shreya Nayak, Vishnu Padmakumar, Vimal Kumar Singh Yadav, and Thockchom Birjit Singha, “Design, Implementation, and Performance Analysis of MUX and Serial-Parallel Architecture-based Novel 4-bit Multiplier” in 12^th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2025.

• Deb, D., Kumari, A., Ignatius, T.M., Singha, T.B., Palathinkal, R.P. (2025). Novel PRNG Design with Seed Updation Policy Using Fibonacci Sequence Generator. In: Guha, K., Saha, S.K., Iannacci, J. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. MNDCS 2024. Lecture Notes in Electrical Engineering, vol 1382. Springer, Singapore. https://doi.org/10.1007/978-981-96-3758-4_28.

• P. Panigrahi, V. R. Rao, T. B. Singha and C. Karfa, "SRIL: Securing Registers from Information Leakage at Register Transfer Level," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 492-498, doi: 10.1109/VLSID60093.2024.00088.

• V. Padmakumar, T. M. Ignatius, T. B. Singha and R. P. Palathinkal, "A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis," 2023 IEEE Silchar Subsection Conference (SILCON), Silchar, India, 2023, pp. 1-6, doi: 10.1109/SILCON59133.2023.10404909.

• J. Santra, A. Kumari, T. M. Ignatius, T. Birjit Singha and R. P. Palathinkal, "A High Speed 32-bit Approximate Adder with Improved Accuracy," 2023 IEEE Silchar Subsection Conference (SILCON), Silchar, India, 2023, pp. 1-6, doi: 10.1109/SILCON59133.2023.10404759.

• Anupam Kumari, Titu Mary Ignatius, Thockchom Birjit Singha, Josephine Sylvester, Roy Paily Palathinkal, “UVM and Python verification environments for RISC-V core” Semiconductor Research Corporation (SRC) TECHCON, Austin, USA, 10-12 September, 2023. 

• T. B. Singha, R. P. Palathinkal and S. R. Ahamed, "Implementation of AES Using Composite Field Arithmetic for IoT Applications," 2020 Third ISEA Conference on Security and Privacy (ISEA-ISAP), Guwahati, India, 2020, pp. 115-121, doi: 10.1109/ISEA-ISAP49340.2020.235009.

• S. Konwar, T. B. Singha and S. Roy, "Power Efficient Code Converters Using Adiabatic Array Logic," 2014 Fourth International Conference of Emerging Applications of Information Technology, Kolkata, India, 2014, pp. 167-172, doi: 10.1109/EAIT.2014.56.

• T. B. Singha, S. Konwar and S. Roy, "Low power design and analysis of fundamental logics using adiabatic array logic," 2014 International Conference on Signal Propagation and Computer Technology (ICSPCT 2014), Ajmer, India, 2014, pp. 775-781, doi: 10.1109/ICSPCT.2014.6884989.

• T. B. Singha, L. Jain and B. Kant, "Negligible time-consuming RC5 remote decoding technique," 2014 International Conference on Computer Communication and Informatics, Coimbatore, India, 2014, pp. 1-4, doi: 10.1109/ICCCI.2014.6921832.

• T. B. Singha, S. Konwar, S. Roy and R. H. Vanlalchaka, "Power efficient priority encoder and decoder," 2014 International Conference on Computer Communication and Informatics, Coimbatore, India, 2014, pp. 1-5, doi: 10.1109/ICCCI.2014.6921806.

• S. Konwar, T. B. Singha, S. Roy and R. H. Vanlalchaka, "Adiabatic logic based low power multiplexer and demultiplexer," 2014 International Conference on Computer Communication and Informatics, Coimbatore, India, 2014, pp. 1-5, doi: 10.1109/ICCCI.2014.6921808.

• Reviewer for the journals:

  • IEEE: Solid-State Circuits Letters, Design & Test 

  • Springer: Circuits, Systems and Signal Processing, Cluster Computing, Discover Computing, and The Journal of Supercomputing 

  • Elsevier: Journal of Systems Architecture, and Microelectronics Journal

• Technical Program Committee (TPC) member and reviewer, International Conference on VLSI Design: Bengaluru, 2027; Pune, 2026; and Bengaluru, 2025.

• Website Chair & Track Chair (Hardware Security), Technical Program Committee (TPC) member, reviewer, IEEE International Conference on Intelligent Computing and Systems at the Edge (ICEdge), IISc Bangalore, December 17-19, 2026.

• Technical Program Committee (TPC) member and reviewer, IEEE International Conference on Intelligent Computing and Systems at the Edge (ICEdge), IISc Bangalore, December 18-20, 2025.

• Technical Program Committee (TPC) member and reviewer, VDAT, 2025, Chandigarh.

• Reviewer, VDAT Conference, 2023.

• Reviewer, 4^th International Conference on Emerging Electronics and Automation (E2A), 2024.

• Invited speaker for “Workshop on VLSI Design” for a hands-on training session on “Xilinx Vivado and FPGA-based digital system design”, organized by Department of Design and Department of Electronics & Electrical Engineering, IIT Guwahati, on 29^th October, 2022 and 5^th November, 2022.

• Active volunteer in organizing an Instruction Enhancement Program (IEP) on “Introduction to Analog & Digital VLSI Design”, April 10-14, 2017, jointly organized by IIT Guwahati and IIT Kharagpur at IIT Guwahati under Special Manpower Development Program - Chip to System Design (C2SD).

• Dedicated volunteer service for 18^th IEEE India Council Annual International Conference (INDICON-2021) held in hybrid mode, 19^th-21^st December, 2021 at IIT Guwahati.

• Served as Editor-in-Chief in the Research Scholar Forum, Department of Electronics and Electrical Engineering, IIT Guwahati for the academic year 2018-19. 

• Successfully mentored two M. Tech. students to bag the “best thesis award” at IIT Guwahati during PhD tenure.

Basic requirements: 

1. Good enough subject knowledge
2. Willingness to learn 
3. Intent to excel in career and life
4. Courtesy and respect for teachers and co-workers

Students with high motivation and interest to work in the following areas are welcome to drop an email to me.

• Chip design
  • Digital circuit implementation of accelerators involved in PQC algorithms (Kyber and Dilithium) [RTL to GDSII flow]
  • Hardware-software co-design of PQC algorithms (Kyber and Dilithium) [Processor + Memory + Accelerators] [RTL to GDSII flow]
  • Countermeasure design (algorithm-agnostic) to thwart power and EM side-channel attacks [Analog and digital perspectives]
  • Side-channel attack (power and EM) detection circuits [Mostly, analog perspective]
• FPGA-based design
  • HDL-based implementation of PQC algorithms (Kyber and Dilithium) and/or its accelerators such as Number Theoretic Transform (NTT), Secure Hash Algorithms (SHA), Coefficient Wise Multiplication (CWM).
• Side-channel attack model design
  • Machine learning-based advanced attack models to perform Correlational Power/Electro-Magnetic Analysis (CPA/CEMA) on crypto-algorithms.
• Mathematics
  • Galois Field (GF) theory, Modular Arithmetic, Lattice-Based Cryptography (LBC), Module Learning With Error (MLWE)