smittal.ece's picture
Dr. Sushant Mittal
Assistant Professor
Department of Electronics Engineering, IIT(BHU)
smittal.ece@iitbhu.ac.in
.
Area of Interest: 
Semiconductor logic and memory devices, Design Technology Co-optimization (DTCO), Variability modeling of devices

  1. B.Tech., Electronics Engineering, Indian Institute of Technology-BHU, Varanasi  in 2008.
    • Prof. A. K. Ghose Silver Medal for overall 2nd rank (2/50) in Electronics Engg. Exam 2008
    • Rank 1/50 in Electronics Engineering Exam in 2007 and 2008.
  2. Ph.D., Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, 2016.
    • Thesis: Challenges in FinFETs: Analytical Modeling and Structural Solutions
    • Advisor: Prof. Udayan Ganguly, IIT Bombay; Co-Advisor: Prof. Saurabh Lodha, IIT Bombay.
  1. July 2020 onwards; Assistant Professor, Electronics Engg., IIT-BHU, Varanasi, India.
    • Research and teaching in Micro-electronics.
  2. April - July 2020; Senior Process Integration Modeling Engineer, Applied Materials India Pvt. Ltd., Bengaluru, India.
    • Physics and computational based modeling of unit processes like etch and deposition.
  3. Dec 2018- March 2020; Physicist/Scientist, Applied Materials India Pvt. Ltd., Bengaluru, India.
    • Device design guidelines for FinFET at 5 and 3 nm technology node for improved performance.
    • Established material to ring-oscillator circuit performance evaluation flow for quick evaluation of impact of BEOL parameters to circuit performance.
    • Circuit Compact Model extraction for FinFET at advanced technology nodes.
  4. April 2017- Dec 2017; CAE Engineer, Applied Materials India Pvt. Ltd., Bengaluru, India.
    • Device design guidelines for FinFET at 14 nm technology node for improved performance.
    • Variability analysis and Line Edge Roughness (LER) guidelines for FinFETs at 14 nm technology node.
    • Variability analysis and process guidelines of Gate All Around (GAA) FET at 14 nm technology node.
    • Process guidelines for 3D NAND
  5. Feb 2016- March 2017; Device Engineer, Micron Semiconductors Pvt. Ltd., Bengaluru, India.
    • Developed physics based analytical models for emerging memory technologies. And validated them against experimental data.
    • Evaluated fabrication flow of next generation 3D NAND
  6. Aug 2008- July 2010; ASIC Design Engineer, Nvidia Graphics Pvt. Ltd., Bengaluru, India.
    • x86 Microprocessor Architecture Verification
      • Lead team of 10s of engineers for timely release of new test cases.
      • Wrote new test cases for verification of processor internal interrupt controller, vector instructions and decode instructions of x86 based microprocessor architecture.
      • Automated new test case generation, release flow, debugging of test cases, and document generation without manual intervention by writing 10s of perl scripts.
      • Characterized several portion of the processor architecture like Advanced Vector Instructions, Processor Internal Interrupt Controller, Performance Monitoring Counters etc.
    • Full- chip Verification of leading discrete GPU chip
      • Rectified several top level failures using Verdi and Siloti.
      • Developed perl scripts to debug corner cases easily at the top level verification environment of the discrete GPU chip.
  7. May- July 2007; Summer Intern with Prof. Nagendra Krishnapura, Electrical Engg., IIT Madras.
  8. May- July 2006; Summer Intern with Prof. Girish Kumar, Electrical Engg., IIT Bombay.

Patents

  1. R. Freed, M. Sachan, S.S. Roy, G. Alva, H-Y. D. Hwang, U. Mitra, E. M. Bazizi, A.B. Sachid, H. Ren, and S. Mittal, “ IP title is Confidential". Filed on USPTO, Sept. 2020.
  2. S. Mittal, A. Pal, E. M. Bazizi, and A.B. Sachid, “Highly doped through-contact Silicon Epitaxy (TS Epi) shapes for reduced source/drain (SD) contact plug resistance”. Filed on USPTO. Application number: 62/909,420
  3. R. Freed, E. M. Bazizi, A.B. Sachid, H. Ren, and S. Mittal, “Via Shape Engineering for reducing and controlling via resistance”. Filed on USPTO. Application number: 62/909,420
  4. U. Ganguly, S. Dutta and S. Mittal, “A Bulk Planar Capacitor-less Dynamic Random Access Memory (DRAM)”, 1976/MUM/2015, Indian Patent Applied.
  5. S. Mittal, S. Gupta, U. Ganguly, A. Nainani, S. Lodha, S. Ganguly, M. Abraham and E.-X. Ping, “Transistor design for improved performance and variability and method of fabrication”, 1750/MUM/2012. Patent Number: 358169, Award Date: Feb 10, 2021, The Patent Office, Govt. of India. 

Journal Publications

  1. S. Mittal, Amita, A.S. Shekhawat, S. Ganguly and U. Ganguly, “Analytical Model to estimate FinFET’s ION, IOFF, SS and VT distribution due to FER”, IEEE Transactions on Electron Devices, vol. 64, no. 8, pp.3489-3493, June 2017. (link)
  2. S. Mittal, A.S. Shekhawat and U. Ganguly, “An Analytical Model to estimate FinFET’s VT distribution due to Fin Edge Roughness”, IEEE Transactions on Electron Devices, vol. 63, no. 3, pp.1352-1358, Jan 2016. (link)
  3. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha and U. Ganguly, “Epitaxially Defined FinFET: Variability Resistant and High Performance Technology”, IEEE Transactions on Electron Devices, vol. 61, no. 8, pp.2711-2718, Aug 2014. (link)
  4. S. Kurude*, S. Mittal* and U. Ganguly, “Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies”, IEEE Transactions on Electron Devices, vol. 63, no 9, pp. 3514-3520, August 2016 (*: equal contribution) (link)
  5. Amita, S. Mittal and U. Ganguly, “The First Compact Model to Determine VT-distribution for DG-FinFET due to LER”, IEEE Transactions on Electron Devices, vol. 65, no 11, pp. 4772-4779, Nov 2018 (link)
  6. P. H. Vardhan, S. Mittal, S. Ganguly, and U. Ganguly, “Analytical Modeling of Metal Gate Granularity based Threshold Voltage Variability in NWFET”, Solid State Electronics, vol. 147, pp. 26-34, Sept 2018 (link)
  7. Amita, S. Mittal and U. Ganguly, “An Analytical Model to Estimate VT distribution of partially correlated fin edges in FinFETs due to Fin-Edge Roughness”, IEEE Transactions on Electron Devices, vol. 64, no 4, pp. 1708-1715, March 2017 (link)
  8. P. H. Vardhan, S. Mittal, S. Ganguly, and U. Ganguly, “Analytical estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET”, IEEE Transactions on Electron Devices, vol. 64, no 8, pp. 3071-3076, June 2017 (link
  9. A. Nainani, M.C. Abraham, S. Mittal, S. Gupta, S. Lodha and U. Ganguly, “Integrating Ge Channel Materials in pMOSFET With Epi-Defined FinFET”, NANOCHIP Technology Journal, Applied Materials Inc., vol. 11, no. 2, pp.8-12, 2013.

Refereed Conferences 

  1. S. Mittal, A. Pal, M. Saremi, E. M. Bazizi, B. Alexander, B. Ayyagiri, “Via Size Optimization for Optimum Circuit Performance at 3 nm node”, accepted in 25th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept 2020, Japan.
  2. B. Ayyagiri, A. B. Sachid, B. Alexander, E. M. Bazizi, V. Reddy, A. Low, J. Ferrell, A. Pal, S. Mittal and M. Saremi “Improving PPAC Through Materials-to-Systems (M2S) Co-Optimization for Emerging Technologies”,  57 th Design Automation Conference (DAC),  2020, San Francisco, USA. (link)
  3. R. Hung, X. Cen, Y. Xu, Y. Lei, K. Wu, W. Lei, S. Mittal, A. Pal, E. M. Bazizi, B. Alexander, T. H. Ha, X. Tang, K. Kashefizadeh, S. Kesapragada, Z. Chen, N. Kim, M. Naik, “Material Innovation for MOL Contact Resistance Reduction with Selective Tungsten”, accepted in 23rd IEEE International Interconnect Technology Conference, (IITC) 2020.
  4. S. Mittal, A. Pal, M. Saremi, J. Ferrell, M. Haverty, T. Miyashita, N. Kim, E. M. Bazizi, B. Alexander, A. B. Sachid and B. Ayyagari, “Highly-Doped Through-Contact Silicon Epi Design at 3 nm node”, 77th International IEEE Device Research Conference (DRC), Jun 2019, Ann Arbor, USA.
  5. A. Pal, S. Mittal, E. M. Bazizi, A. B. Sachid, M. Saremi, B. Colombeau, G. Thareja, S. Lin, B. Alexander, S. Natarajan and B. Ayyagari, “Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node”, 24th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept 2019, Udine, Italy. (link)
  6. T. Miyashita, S. Mittal, M. Kim, A. Pal, A. Sachid, K. Pathak, and M. Cogorno, “FinFET Extension Towards N3 and Beyond- Local Fin Trimming”, 2019 International Conference on Solid State Devices and Materials (SSDM), Aichi, Japan, 2019. (Invited)
  7. T. Miyashita, S. Sun, S. Mittal, M.S. Kim, A. Pal, A. Sachid, K. Pathak, M. Cogorno, and N.S. Kim, “Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond”, 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2018. (link)
  8. A. Pal, S Mittal, B. Ghosh, C.Y. Lin, B. Alexander, B. Ayyagari and A.B. Sachid, “Scaling NC-FinFET to Sub-3 nm Nodes”, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, San Francisco, 2018. (link)
  9. S. Mittal, A.S. Shekhawat and U. Ganguly, “FinFET Scaling Rule Based On Variability Considerations”, 73rd International IEEE Device Research Conference (DRC), Jun 2015, Columbus, Ohio, USA. (link)
  10. S. Mittal, S. Kurude, S. Dutta, P. Debashis, S. Ganguly, S. Lodha, A. Laha and U. Ganguly,  “Epitaxial Rare Earth Oxide (EOx) FinFET: a variability-resistant GeFinFET architecture with multi VT”, 72nd International IEEE Device Research Conference (DRC), Jun 2014, Santa Barbara, USA. (link)
  11. S. Mittal*, S. N. Chinta*, P. Debashis and U. Ganguly, “A FinFET LER VT variability estimation scheme with 300x efficiency improvement”, 19th International IEEE Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2014, Yokohama, Japan. (*:equal contribution) (link)
  12. S. Dutta, S. Mittal, S. Lodha, J. Schulze, and U. Ganguly, “A Bulk Planar SiGe Quantum-Well based ZRAM with low VT Variability”, 7th International Memory Workshop (IMW), May 2015, Monterey, CA,USA. (link)
  13. P. H. Vardhan, S. Mittal, A. S. Shekhawat and U. Ganguly, “Analytical modeling of Metal gate granularity induced Vt variability in NWFETs”, 74th IEEE Device Research Conference (DRC), 2016. (link)
  14. S. Mittal, S.Lodha and U. Ganguly, “Circuit Area Improvements in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs”, 18th International Workshop on Physics of Semiconductor Devices (IWPSD) 2015, India
  15. S. Mittal*, A.S. Shekhawat* and U. Ganguly, “Weakness in Impedance Field Method for RDF variability: A Case for Atomistic Simulator Development”, 18th International Workshop on Physics of Semiconductor Devices (IWPSD) 2015, India. (*: equal contribution)
  16. P. Bhatt, P. Swarnkar, S. Mittal, F. Basheer, C. Thomidis, C. Hatem, B. Colombeau, N. Variam, A. Nainani and S. Lodha, “Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs”, 72nd International IEEE Device Research Conference (DRC), Jun 2014, Santa Barbara, USA. (link)
  17. P. Debashis, S. Mittal, S. Lodha and U. Ganguly, “Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs”, 21st International IEEE Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Taiwan, 2014. (link)
  18. S. Mittal, P. Debashis, A. Nainani, M. C. Abraham, S. Lodha and U. Ganguly, "Epi Defined (ED) FinFET with Dynamic Threshold: Reduced VT Variability, Enhanced Performance, and a novel Multiple VT”, IEEE India Conference (INDICON), Dec 2013, Mumbai, India. Won Best Paper Award. (link)
  19. S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha and U. Ganguly, “Epi Defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET”, 6th International IEEE Nanoelectronics Conference (INEC), Jan 2013, Singapore. (link)
  20.  S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha and U. Ganguly, “Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT”, IEEE Device Research Conference (DRC), Jun 2012, Pittsburgh. (link)
S/ No. Name of Award Awarding Agency Year
1 Best Paper Award in IEEE India Conference (INDICON) 2013 in Signal Processing and VLSI category. IEEE India Council and IEEE Bombay Section 2013
2 Featured in the IEEE list of Golden reviewers for IEEE Transactions on Electron Devices (2015 and 2016) and IEEE Electron Device letters (2020), two premier journals of IEEE on electron devices. IEEE 2015, 2016, 2020
3 O P Jindal Engineering and Management Scholar 2007 O P Jindal Group 2007
4 Prof. A. K. Ghose Silver Medal for standing second in B.Tech. Part IV Electronics Engineering Examination. IT-BHU (now IIT-BHU, Varanasi) 2008
5 1st position in B.Tech. Part III, Electronics Engineering Examination, IIT-BHU, 2006-07 IT-BHU (now IIT-BHU, Varanasi) 2007
6 10th Rank in Regional Mathematics Olympiad (RMO) 2002, Uttarakhand. National Board of Higher Mathematics & Department of Atomic Energy, Govt. of India 2002
7 All India Rank 475 in 6th National Science Olympiad 2003 Science Olympiad Foundation 2003
8 6th Rank in Uttarakhand in Class XII examination (AISSCE 2004) Shri N.D. Tiwari, former Chief Minister of Uttarakhand 2004
9 Best Innovative Fresher Award in Technex 2005, IT-BHU (now IIT-BHU) Gymkhana, IT-BHU (now IIT-BHU) 2005
10 1st position in MODEX (Industrial Applications and Experimentation category), Technex 2006, IT-BHU (now IIT-BHU) Gymkhana, IT-BHU (now IIT-BHU) 2006
11 First Prize in Prastuti’06, an all-India paper presentation contest conducted at IT-BHU (now IIT-BHU). IEEE and IEE (UK) at IT-BHU (now IIT BHU). 2006
12 Second Prize in Prastuti’07, an all-India paper presentation contest conducted at IT-BHU (now IIT-BHU). EES-IT-BHU at IT-BHU (now IIT BHU). 2007
13 One of 29 candidates nationwide qualified for final stage of KVPY (Kishore Vaigyanik Protsahan Yojana) 2005. KVPY Cell, IIT Bombay 2005
  1. "Modeling Variability in FinFETs - Part I and II”, AICTE Sponsored short-term course on "Nanoelectronics Devices and Circuits" , IIT-BHU, Varanasi, January 2021.
  2. "FinFET based SRAM cell evaluation at advanced technology nodes- Workflow and Initial Study”, XXth International Workshop on The Physics of Semiconductor Devices (IWPSD 2019), Kolkata, December 17-20, 2019. (link)
  3. “Modeling Variability in FinFETs- From Devices to Circuits”, Synopsys Users Group 2018 (SNUG 2018), Bengaluru, July 12, 2018. (link)
  4. “FinFET Variability Modeling in IOT Era”, IEEE Workshop on Compact Modeling, IIT Kanpur, March 3’ 2017. (link)
  5. Indian Nanoelectronics User Program (INUP) Hands-On Training Workshop, IIT Bombay, Mumbai
    1. "Device Simulation using TCAD"                                                                                                                            Jul ‘14
    2. "TCAD for Experimentalist"                                                                                                                                    Aug ‘14
    3. "Challenges in FinFET transistors-solutions and modeling"                                                                                   Sep ‘14
  6. NVIDIA Graphics Pvt. Ltd., Bengaluru, India
    1. "NVIDIA TESLA Frame Buffer"                                                                                                                              Mar ‘09
    2. "Segmentation and Paging in x86 architecture"                                                                                                        Jun ‘09
    3. "IA 32 Decode Unit"                                                                                                                                                 Aug ‘09
  7. "Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT", poster at IBM Technology Day at IIT Bombay, November 2012
  8. "Simulation and Modeling of Ge Trigate Devices" poster at Applied Materials-IIT Bombay partnership program at IIT Bombay, Mumbai, April 2011