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Dr. Kishor P. Sarawadekar
Assistant Professor
Department of Electronics Engineering Indian Institute of Technology
skishor.ece@iitbhu.ac.in
+91-9838764487
Area of Interest: 
Algorithms and Architectures for Image/Video Signal Processing, Image Coding Systems, Biomedical Image Processing and VLSI Based Signal Processing

Ph.D. (Electronics and Electrical Communication Engineering) 
Dissertation: VLSI Based Performance Enhancement of Image Processing Units for an Ultrasound System,
Indian Institute of Technology, Kharagpur, 2012.

M. Tech. (Electronics and Electrical Communucation Engineering),
Specialization: VLSI Design and Microelectronics Engineering, 
Indian Institute of Technology, Kharagpur, 2007.

B. Tech. (Electronics Engineering),
Shivaji University, Kolhapur, Maharashtra, 1996.
 

  • Assistant Professor        Indian Institute of Technology, Varanasi                               Since June 2014 
  • Assistant Professor            Defence Institute of Advanced Technology, Pune                           Oct. 2013 - May 2014
  • Software Engineer-II         Xilinx India Technology Services Pvt. Ltd., Hyderabad                    July 2011  - Sept.2013
  • Sr. Research Fellow           SRIC - IIT Kharagpur                                                                  Dec. 2007 - June 2011
  • Lecturer                           Don Bosco Institute of Technology, Kurla, Mumbai                         July  2002 - Dec. 2007
  • Design Engineer                V3 Logic Pvt. Ltd., Pune                                                              July  2001 - June 2002
  • Lecturer                           Vidhyavardhini’s College of Engineering, Mumbai                           July  1998 - Feb. 2001
  • Marketing Executive          Vinit Electronics Pvt. Ltd., Pune                                                    May 1997 - July 1998

Spring 2018:

  • EC562: Digital Designing and Modeling with VHDL
  • EC596: Sensor Systems Lab. II

Journals:

  • Subiman Chatterjee and Kishor Sarawadekar, “An Optimized Architecture of HEVC Core Transform using Real-Valued DCT Coefficients,” IEEE Transactions on Circuits and Systems--II: Express Briefs, Accepted for publication, Early Access, DOI: 10.1109/TCSII.2018.2815532
  • Gourav Modanwal and Kishor Sarawadekar, “A New Dactylology and Interactive System Development for Blind–Computer Interaction,” IEEE Transactions on Human-Machine Systems, Accepted for publication, Early Access, DOI: 10.1109/THMS.2017.2734065 
  • Gourav Modanwal and Kishor Sarawadekar, “Towards hand gesture based writing support system for blinds,” Pattern Recognition, vol. 57, pp. 50–60, Sept. 2016
  • Kishor Sarawadekar, R. Biswas, Srinivas Varna and S. Banerjee, “An FPGA-based architecture of DSC–SRI units specially for motion blind ultrasound systems,” Journal of Real Time Image Processing, vol. 10, issue 3, pp 573 - 595, 2015
  • Kishor Sarawadekar and S. Banerjee, “Area Efficient, High Speed EBCOT Architecture for Digital Cinema,” ISRN Signal Processing, vol. 2012, Article ID 714176, DOI: 10.5402/2012/714176
  • Kishor Sarawadekar, D. Bera, H. B. Indana, and S. Banerjee, "VLSI-DSP based real time solution of DSC-SRI for an ultrasound system," Journal of Embedded Hardware Design (Microprocessors and Microsystems), vol. 36, no. 1, pp. 1–12, Feb. 20122
  • Kishor Sarawadekar and S. Banerjee, "VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000," Integration, the VLSI Journal, vol. 45, no. 1, pp. 1–8, Jan. 2012
  • Kishor Sarawadekar and S. Banerjee, "An efficient pass-parallel architecture for embedded block coder in JPEG 2000," IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 6, pp. 825–836, Jun. 2011

Conference:

  • Gourav Modanwal and Kishor Sarawadekar, "A Gesture Elicitation Study with Visually Impaired Users," in the 20th International Conference on Human-Computer Interaction Las Vegas, Accepted for Publication
  • Gourav Modanwal and Kishor Sarawadekar, “A Robust Algorithm for Hand-forearm Segmentation,”in the International Conference on Image and Graphics Processing (ICIGP 2018), Hong Kong, February 24-26, 2018
  • Subiman Chatterjee and Kishor Sarawadekar, “Constant Throughput HEVC Core Transform Design,” in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, UAE, October 2016
  • Subiman Chatterjee and Kishor Sarawadekar, “A Low Cost, Constant Throughput and Reusable 8X8 DCT Architecture for HEVC,” in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, UAE, October 2016
  • Gourav Modanwal and Kishor Sarawadekar, “Development of a New Dactylology and Writing Support System Especially for Blinds,” in 13th International Conference on Computer and Robot Vision, Victoria, British Columbia, Canada, June 2016, 362-369
  • Kishor Sarawadekar, R. Biswas, and S. Banerjee, "DSC-SRI algorithms for motion blind detection of objects in an ultrasound system," in The IASTED International Symposia on Imaging and Signal Processing in Healthcare Technology (ISPHT’11), Washington DC, USA, May 2011, pp. 69-76
  • Kishor Sarawadekar, O. Kulkarni, and S. Banerjee, "VLSI implementation of MQ decoder in JPEG 2000," in IEEE Students’ Technology Symposium (TechSym’11), IIT Kharagpur, India, Jan. 2011, pp. 193-197
  • Kishor Sarawadekar and S. Banerjee, "Low-cost, high-performance VLSI design of an MQ coder for JPEG 2000,” in 10th IEEE International Conference on Signal Processing (ICSP’10), Beijing, China, Oct. 2010, pp. 397–400
  • Kishor Sarawadekar and S. Banerjee, "Area efficient, high-speed VLSI design for EBCOT block coder in JPEG 2000," in IEEE International Conference on Electronics and Information Engineering (ICEIE’10), Kyoto, Japan, Aug. 2010, pp. V2–110–V2–113
  • Kishor Sarawadekar and S. Banerjee, "Efficient VLSI architecture for bit plane encoder of JPEG 2000," in IEEE International Conference on Image Processing (ICIP’09), Cairo, Egypt, Nov. 2009, pp. 2805 – 2808
  • Kishor Sarawadekar and S. Banerjee, "A high speed bit plane coder for JPEG 2000 and its FPGA implementation," in 17th European Signal Processing Conference (EUSIPCO’09), Glasgow, Scotland, Aug. 2009, pp. 2231 – 2234